The present invention relates generally to an electrostatic discharge (ESD) protection for integrated circuit (IC), and more specifically to a substrate pump circuit and method for input/output (I/O) ESD protection in an integrated circuit.
Complementary metal-oxide-semiconductor (CMOS) integrated circuit devices are vulnerable to ESD induced failure. Especially, the applications of thin gate oxide, short channel and shallow junction for high integration density as well as the lightly doped drain (LDD) and self-aligned silicide (salicide) further degrade the performance of MOS devices against ESD. Various techniques have been disclosed to self-protect output buffers or other I/O pads against ESD failures. Some of these measures include diode clamps, lateral punch-through devices and guard ring collectors around an I/O pad, and these circuits are reasonably effective to protect the integrated circuit devices.
ESD protection structures are classified into two categories including structures to protect input buffers and structures to protect output buffers and I/O pads. Protection of input buffers is relatively simple because a CMOS gate does not conduct current. Accordingly, a special protection structure is implemented on the input buffer that restricts the gate voltage of a transistor to a maximum breakdown voltage. To the contrary, the other category of output buffers and I/O pads includes structures that are more difficult to protect. This difficultly results from that the output buffer may conduct current by ESD stress and thus may be damaged. The protection structure must be designed and layout constructed so that the protection structure discharges the ESD stress without self-damage while the output buffer conducts only a minimum current under ESD stress conditions. Two well-known ESD protection structures substantially utilize the transistor turn-on mechanism and the transistor snapback mechanism in the protection circuit, where the former is characteristic of the threshold voltage for channel conduction, and the latter is characteristic of the transistor breakdown voltage. The more popular snapback mechanism is the introduction of an ESD protection structure such as NMOS transistors onto the interconnection between the I/O pad and the internal or core circuit. Upon ESD event, the internal circuit is protected by bypassing of the built-in parasitic bipolar transistors. To release large amount of ESD current by the NMOS transistors without excessive gate width structure, fingers layout is employed for the ESD protection circuit. Unfortunately, the fingers of NMOS transistors are hardly to turn on uniformly due to the inherent structure difference resulted from the fingers arrangement, resulting in that the ESD current will concentrate in a small region and thus burn out the device. As such, even a large ESD protection device will not have acceptable performance. In other proposed solutions substrate pump circuit is used to lower the triggering voltage of NMOS fingers, in order to enhance the turn-on uniformity. To pump the substrate potential, a pumping apparatus has to be turned on before the ESD protection circuit is turned on during an ESD event. However, the pumping transistor may be damaged by the ESD current if its width is small, thus the pumping transistor must be large enough to support the ESD current and the substrate pump circuit will consequently consume a large chip area, which is disadvantageous to scale down and cost down. It is therefore desired a substrate pump circuit of small size for I/O ESD protection.
One object of the present invention is to provide a substrate pump circuit and method for I/O ESD protection including NMOS fingers connected to the interconnection between an I/O pad and an internal circuit, by which an unused PMOS finger in an integrated circuit serves as a pumping apparatus and is turned on to conduct a pumping current through the substrate resistor to a ground pad during an ESD event to thereby pull up the potential of the substrate adjacent to the NMOS fingers so as to reduce the triggering voltage of the NMOS fingers.
In a preferred embodiment, according to the present invention, the NMOS fingers for ESD protection are connected to the interconnection between the I/O pad and the internal circuit, the base of the NMOS fingers is grounded to a ground pad via the substrate resistor, the source of the PMOS finger is connected to the interconnection between the I/O pad and the internal circuit, and its drain is connected to the base of the NMOS finger, and a switch is connected to the gate of the PMOS finger. During normal operation, the PMOS finger is turned off by the switch. When an ESD event happens and causes the voltage on the I/O pad to rise rapidly, the PMOS finger is turned on by the switch to conduct a small ESD current to pump the substrate, and hence the NMOS fingers are turned on uniformly and release most of the ESD current.